FIG. 1 regards to a 8 mm video tape recorder and shows a pattern of helical track to be formed on the magnetic tape. In FIG. 1, the helical track has a video area with the length to correspond to 180 degree winding angles and a PCM area formed next to the video area and a V-P guard area. This PCM area contains a VSC area, a PCM data area and a PCM clock run-in area from nearest to the V-P guard area. In the video area, an FM video signal and an FM audio signal are recorded with frequency multiplied. In the PCM area, PCM audio data is recorded. In the PCM clock run-in area, clock necessary to reproduce the PCM data is recorded.
The VSC area and the V-P guard area are illustrated in FIG. 1 in enlarging a part of them. The VSC area is formed in a part of postamble and the V-P guard areas. A spacing of 0.1H between the edge of the PCM data and the edge of the VSC area is provided. At the other side edge of the VSC area and the edge of the video area, normally in the case of an NTSC system, a spacing of 2.3H is provided and in the case of a PAL system, a spacing of 2.8H is provided.
The VSC area is divided into three areas, i.e., an erase code area to record an erase code, 1.0H search mark area to record a search mark and 0.8H data area to record data. Five data blocks and one end block, a total of six blocks is recorded in the data area. The end block is constituted by 36 bits data and the end code showing that is the last data of the VSC area is recorded.
Each data block is constituted by 51 bits data and 3 bits synchronized code "S" is arranged at the head and in back of it, 6 words consisting of 1 byte (=8 bits) are arranged. The predetermined data are recorded on the first 5 words WD0 to WD4 and the error detection code is placed on the last word CRCC.
FIG. 2 illustrates the construction of a tape recorder which records VSC signals in the VSC area. A switching pulse detection circuit 1 detects the edge of switching pulse (SWP) which shifts the rotary head and outputs the detected signals thereof, to a periodic measuring counter 2. The periodic measuring counter 2 counts the clock to be outputted from the built-in oscillator and resets this count value whenever the detected signals from the switching pulse detection circuit 1 are inputted. And it also supplies the count value Yn-1 just before resetting to the subtracter 3 and simultaneously supplies the count value at an optional point of time to a coincidence detection circuit 5. A subtracter 3 subtracts the value set in advance Xn from the output Yn-1 of the periodic measuring counter 2 and outputs its difference (Yn-1-Xn). This output is latched at a latch circuit 4 and is outputted to a coincidence detection circuit 5.
The coincidence detection circuit 5 outputs coincidence signal when the count value of the periodic measuring counter 2 coincides with the value latched by the latch circuit 4. This coincidence signal is supplied to a VSC data generator 10 as a start pulse and simultaneously supplied to the reset terminal of flip-flop 7 and the set terminal of flip-flop 8. A Pn detection circuit 6 detects the data end from the PCM data to be inputted and supplies the detected signal to the set terminal of flip-flop 7. The signal to be outputted from the Q terminal of flip-flop 7 is supplied to a switch 11 and the switch 11 is "ON" when the Q output of flip-flop 7 is at "H" level and is "OFF" when the Q output is at "L" level. The erase code to be outputted from a erase code generator 9 is supplied to the rotary head (not shown) via the switch 11.
The VSC data generator 10 generates a VSC data when the start pulse is supplied from the coincidence detection circuit 5 and outputs to a switch 12. Also, when the VSC data is finished, it generates the stop pulse and supplies it to the reset terminal of flip-flop 8. The switch 12 is "ON" when the Q output of flip-flop 8 is at "H" level and "OFF" when at "L" level.
FIGS. 3 and 4 explain the function thereof. At first, the edge of switching pulse is detected at the step SP1. When the edge is detected, it proceeds to the step SP2 and the count value Yn-1 is computed at the point of time of the periodic measuring counter 2. And further it proceeds to the step SP3 and Yn-1-Xn will be computed.
More specifically, the periodic measuring counter 2 outputs the count value Yn-1 at the point of time when the switching pulse detection circuit 1 outputs the detection pulse to the subtracter 3. As shown in FIG. 4, this count value Yn-1 corresponds to the length of one field immediately before (the period of time from the rising edge of head switching pulse (or falling edge) to the falling edge (or rising edge)). The subtracter 3 subtracts Xn from this value Yn-1. As shown in FIG. 4, this Xn corresponds to the length from the position to start the VSC signal recording to the rising or falling edge of the head switching pulse. This value is set at a constant value. Therefore, Yn-1-Xn corresponds to the length from the edge immediately before of the switching pulse to the position of VSC signal recording is started. This value will be latched at the latch circuit 4.
Furthermore, the PCM data end is detected at the step SP4. When the PCM data end is detected, it proceeds to the step SP5 and recording of the erase code will be started. Then, at the step SP6 when it is judged that the count value of the periodic measuring counter 2 coincides with Yn-1 computed at the step SP3, it proceeds to the step SP7 and the erase code recording is finished. Then, it proceeds further to the step SP8 and records the VSC signal for 5 blocks.
More specifically, when the Pn detection circuit 6 detects the PCM data end, flip-flop 7 is set and the Q output becomes "H" level and the switch 11 is "ON". As a result, the erase code to be outputted from the erase code generator 9 is supplied to the rotary head (not shown) via the switch 11 and recorded on the erase code recording area of postamble and VSC areas.
On the other hand, when the count value of the periodic measuring counter 2 coincides with the value Yn-1-Xn latched by the latch circuit 4, (as shown in FIG. 4, at the time when the record starting position of the VSC signal arrives) the coincidence detection circuit 5 outputs the coincidence signal. Thus, flip-flop 7 is reset, the switch 11 is "OFF" and recording of the erase code is stopped. Also, since the VSC data generator 10 starts to generate the VSC signal by coincidence signal and flip-flop 8 is set and the switch 12 is "ON", the VSC data generated from the VSC data generator 10 is supplied to the rotary head and recorded as the search mark and VSC data. When the VSC data generator 10 generates all data to record on the VSC area, the stop pulse is generated and flip-flop 8 is reset. With this arrangement, the switch 12 is "OFF" and the recording function to the VSC area is stopped.
In the video tape recorder, there is following problems in that the recording of the VSC signal is to start at the timing after the elapse of fixed time from the edge generating timing of head switching pulse.
As shown in FIG. 5, the generating position of the edge of head switching pulse is given a tolerance of 0.8H and also a tolerance for the position gap of the PCM data end is 1.5H. As a result, the PCM data end delays 1.5H in the worst case, and if the generating timing of the head switching pulse becomes 0.8H faster, as shown in FIG. 5, the recording period of erase code becomes 0.3H (=6.8-1.5-0.8-1.8-2.3-0.1). Thus, if the recording period of erase code becomes extremely short, it is difficult to detect the PCM data end correctly. There is also a problem in that the gap from the standard position of recording position of the VSC signal has become big.